It is well known in the semiconductor art that the performance of MOS transistors can be enhanced by creating a suitable strain (also referred to herein as stress) in the channel region, thereby producing a so-called strained channel transistor. For example, the performance of an n-channel transistor can be enhanced by creating a tensile strain in the channel region of the transistor, and the performance of a p-channel transistor can be enhanced by creating a compressive strain in the channel region of the transistor.
Some conventional strained channel transistors use a stressor positioned in the channel region to create the desired stress. The use of a stressor positioned in the channel region is described, for example, in U.S. Pat. No. 6,492,216, which is incorporated herein by reference. Other conventional strained channel transistors use stressors positioned laterally of the channel to create the desired stress. The use of stressors positioned laterally of the channel is described, for example, in U.S. Patent Application Publication No. 2005/0035409, which is incorporated herein by reference.
In view of the performance advantage associated with strained channel transistors, it is desirable to provide for strained channel transistors with channel strain characteristics, and associated performance enhancements, that exceed those that are conventionally available.